Not Applicable.
The present invention relates to the field of data communications, and more particularly, to the field of data alignment in a communications system.
In data communications, data is generally transmitted in a serial communications format through current networks. It is often the case that the data to be transmitted between two data endpoints is packaged according to specific data communications protocols to facilitate the transmission across the particular network in question. This packaging may include the addition of network management and other information such as headers and trailers to the data to facilitate transmission based upon the dictates of the particular protocol employed. Such packaging is generally termed xe2x80x9cframingxe2x80x9d in the art.
Some of these protocols may include, for example, data transmission using time division multiplexing (TDM) approaches such T1 and E1 standards known in the art. Other example standards may include high-level data link control (HDLC) or asynchronous transfer mode (ATM). Each of these protocols have their own applications and goals in terms of history, performance, error-immunity, flexibility, and other factors. Consequently, each of these protocols employ framing procedures by which data is packaged for transmission across the various networks employed. These protocols are generally incompatible and require translation or conversion to transmit data in a transmission link that employs two or more protocols in two or more different segments.
The conversion from one protocol to another requires specific framing technology to accomplish the task. With a myriad of standards between which conversion is possible, many different dedicated protocol conversion units have been developed to accomplish the specific conversion tasks presented. The typical protocol conversion unit is labeled xe2x80x9cdedicatedxe2x80x9d above because such units generally employ dedicated circuits which are capable only of performing the conversion from one specific protocol to another. The result of this fact is a multitude of protocol conversion units on the market to accomplish the individual conversion tasks, thereby diminishing efficiencies to be obtained by mass production.
It is also the case that new communications standards are developed as data communication technology develops over time. Often times, a particular standard may be in flux while discussion ensues among those skilled in the art until agreement on concrete provisions articulating a standard is reached. Consequently, it is difficult to develop data communications technology that employs an up and coming standard until the standard is settled. In the competitive world of data communications technology production, it is desirable to produce products to meet these new standards as quickly as is possible after a standard is finalized so as to compete in the marketplace.
It is an objective of the present invention to provide for technology which can achieve protocol conversions between any number of protocols to obtain the efficiencies of mass production and feature the flexibility allowing the unit to be quickly adapted to new data communications protocols as they develop. In addition, there is a second objective to provide for corresponding circuits which can perform specific tasks in conjunction with the aforementioned protocol conversions. For example, some protocols require the performance of byte alignment and other similar functions.
In furtherance of these and other objectives, the present invention entails a parallel-to-serial-to-parallel (PSP) circuit that interfaces with a data bus, preferably with a processor, for byte alignment and other operations. The PSP circuit includes an input bit shift register having a predetermined number of register positions and an output bit shift register with the same number of register positions. The output of the input bit shift register is fed into the output bit shift register through a multiplexer. The input bit shift register may receive a bit write from a bit bus, a partial parallel write from a data bus with corresponding data validity data received on a shadow bus, and full parallel write from the data bus. The output bit shift register may transmit a bit read to the bit bus or a full parallel read to the data bus. Data received is shifted to the output bit shift register and compiled into full parallel data or read out as single bits. Offset bits may be introduced in the data stream for data alignment. The present invention also provides a further advantage of including the ability to perform various bit stuffing and bit scrambling operations.
In accordance with another aspect of the present invention, a method is provided for achieving byte alignment and other objectives, comprising the steps of reading a predetermined number of bits from a data bus, the predetermined number of bits being out of alignment relative to the data bus. Secondly, the step of shifting the predetermined number of bits into alignment with the data bus is performed, and finally the aligned data is written to the data bus in either a fill parallel write or to the bit bus in a bit write.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the claims.